Here's everything at 0 degrees. Note that all degrees are in reference to the 16x bitclock. With these phases, the system could work.
Now we've retarded the receiver's clock by 45 degrees. Everything is still working.
Now we've retarded the recevier's clock by 90 degrees, with reference to the transmitter's clock. Note that all data bit changes are still perfectly in time with the rising edges of the transmit bit clock. It still works at this point, but not by much margin. Also note that the received data is inverted!
Now we've retared the edges of the data by 45 degrees (45 degrees of a clock cycle). Here we see that under these conditions, it is imposible for the system to detect an edge change in the data stream. Note that due to the timing, the output of XOR gate has a perfect 50% duty cycle, and this causes the integrator to always read "Half".
Now we've moved the receive clock ahead another 45 degrees, to 135. It is once again working, but the data is inverted.
Here the receive clock phase is 180 ahead (or behind, have it your way!) of the transmit clock. Everything is decoding again, except the data is inverted.